1. Field of the Invention
The present invention relates to growth of semiconductor materials and devices, and more particularly, to heteroepitaxial growth of a first semiconductor (such as gallium arsenide) on a masked second semiconductor (such as silicon dioxide masked silicon) and devices in such heterostructures.
2. Description of the Relates Art
Many researchers have investigated growth of semiconductordevice quality gallium arsenide (GaAs) on silicon wafers and fabrication of active devices in the GaAs. Such devices would combine the higher mobility of carriers in GaAs with the greater mechanical strength and thermal conductivity of a silicon substrate. For example, R. Fischer et al., GaAs/AlGaAs heterojunction Bipolar Transistors on Si Substrates, 1985 IEDM Tech. Digest 332, report GaAs/AlGaAs heterojunction bipolar transistors grown on silicon substrates and having current gains of .beta.=13 for a 0.2 .mu.m thick base. Similarly, G. Turner et al, Picosecond Photodetector Fabricated in GaAs Layers Grown on Silicon and Silicon On Sapphire Substrates, 1985 IEDM Tech. Digest 468, report response times of 60 picoseconds for photoconductive detectors fabricated in GaAs on silicon. These articles also note that majority carrier devices such as MESFETs fabricated in GaAs on silicon have performance approaching that of homoepitaxial devices; and this has encouraged efforts to integrate GaAs/AlGaAs optoelectronic and high-frequency devices and silicon devices on the same wafer to utilize high-data-rate optical interconnections to reduce the number of wire interconnections. Selective recrystallization of amorphous GaAs can use the high resistivity of noncrystalline GaAs; see, for example, A. Christou et al., Formation of (100) GaAs on (100) Silicon by Laser Recrystallization, 48 Appl. Phys. Lett. 1516 (1986).
One of the principal reasons for the increasing activity in the epitaxial growth of GaAs on silicon substrates is the prospect of monolithic integration of GaAs and Si devices in the same structure. In order to achieve this goal, however, it will be necessary to develop materials growth and device processing techniques that will permit the coexistance of circuit elements with vastly different fabrication requirements. One of the most promising of these approaches is the patterned growth of GaAs onto a silicon substrate through openings in a protective mask of either silicon nitride (Si.sub.3 N.sub.4) or silicon dioxide (SiO.sub.2). In this scheme, the fabrication of the silicon based devices (which typically require high temperature processing) would be completed prior to the deposition of a protective oxide or nitride overlayer. Single crystal GaAs could then be grown into lithographically defined holes in the overlayer, and GaAs device fabrication would follow.
Previous work has established that epitaxial GaAs can be successfully deposited onto silicon substrates through a patterning mask; see B. Y. Tsaur et al., 41 Appl Phys. Lett. 347 (1982), P. Sheldon et al., 45 Appl. Phys. Lett. 274 (1984), Daniele et al., U.S. Pat. No. 4,587,717, and Betsch et al., U.S. Pat. No. 4,551,394. In addition, the integration of Si and GaAs device structures via this technology has been demonstrated; see H. K. Choi et al., 7 IEEE Elec. Dev. Lett 241 and 500 (1986) and H. K. Choi et al., Heteroepitaxy on Silicon, J. C. C. Fan and J. M. Poate Eds., 67 MRS Symposia Proceedings 165 (1986).
It is now well established that the differences in lattice parameters and thermal expansion coefficients that can limit the performance of GaAs devices. This situation would be exacerbated when the GaAs is deposited through holes in a mask onto a silicon surface by molecular beam epitaxy (MBE). Due to the nonselective nature of MBE growth, the single crystal GaAs regions would be in intimate contact with the polycrystalline GaAs that would grow on the amorphous mask material. The presence of this extra defective interface would naturally be expected to serve as a source for addition crystallographic defects. Similar effects are expected with other growth methods such as metalorganic chemical vapor deposition (MOCVD).
The simplest avenue for the patterned growth of GaAs on Si would involve the epitaxial growth of the GaAs onto the original planar silicon surface. however, the final level of the GaAs surface where device fabrication occurs may be several microns above the the level of prefabricated silicon devices. This situation would naturally complicate the interconnect of the two devices structures by conventional metallization schemes. Indeed, for integrated circuits with both digital silicon and digital GaAs devices on an underlying silicon substrate, the coplanarity between the surface of the GaAs regions and the surface of the silicon substrate is essential. One method to achieve this coplanarity is by forming recesses in the silicon substrate where the GaAs regions are to be located and then growing a GaAs layer until the surface of the GaAs in the recesses is coplanar with the surface of the silicon substrate outside of the recesses. Typically the recesses will be about two to three microns deep; see FIG. 1 for a cross sectional elevation view in which the recess was defined by an silicon dioxide (oxide) mask and a layer of GaAs grown by molecular beam epitaxy (MBE) without removal of the oxide mask. The portion of the GaAs layer over the silicon substrate grows as a single crystal beyond a thin dislocation region along the interface, whereas the portion of the GaAs layer over the oxide mask grows as polycrystalline GaAs.
In order to complete a coplanar GaAs in recesses in a silicon substrate, the polycrystalline GaAs in FIG. 1 must be removed without affecting the single crystal GaAs in the recess. The standard method is photolithography: apply photoresist and pattern it to just cover the single crystal GaAs in the recess; then etch off the polycrystalline GaAs using the patterned photoresist as the etch mask. however, this has an alignment problem for the patterned photoresist mask, which is aggravated by the step in the GaAs layer at the recess edge. In particular, if the patterned photoresist mask is offset or of the wrong size, then either the single crystal GaAs is eroded or not all of the polycrystalline GaAs is removed (or both) which disrupts coplanarity. FIG. 2 shows both the groove in the single crystal GaAs at a recess edge and the polycrystalline GaAs strip at another recess edge resulting from an offset mask; the groove can be as deep as two microns and the strip can be as high as two or three microns. Both the groove and the strip are incompatible with standard metal interconnection processing.
Thus the known planarization methods for GaAs regions in a silicon substrate have the problems of grooves in the GaAs and strips of GaAs at the interface with the silicon.
Selective epitaxial growth of heavily-doped regions of GaAs in recesses of an essentially undoped GaAs substrate by MBE with a lift-off process is known. The heavily-doped regions could be the source and drain regions for a FET. See A. Cho et al., Selective Lift-Off for Preferential Growth with Molecular Beam Epitaxy, 24 IEEE Tr.Elec.Dev. 1186 (1977).